1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly but not exclusively to the protection of integrated circuit gates during fabrication.
2. Description of the Background Art
In the manufacture of semiconductor devices, physical vapor deposition (PVD, also known as sputtering) is commonly used to deposit thin films of metal on a silicon substrate. This process involves conversion of target material into vapor phase by ion bombardment. The bombarding ion used is typically an inert gas, such as Argon. The property of inertness is important because it does not react with other species. In order for material to become a bombarding species it must gain sufficient energy and be directed towards a target metal. The inert gas atoms gain sufficient energy through the ionization process in a plasma. A plasma or glow discharge is an energetic ionized gas generated by electric discharge in a gaseous medium. The PVD process may take ten to thirty seconds, so voltage buildup may be in the order of tens of volts in the last few seconds of the process. A PVD process in one exemplary embodiment is schematically illustrated in FIG. 1, where plasma 112 allows for deposition of metal from a target 110 onto a silicon wafer substrate 114. During this processing step, relatively high charges can buildup on existing metal layers on the silicon substrate.
As process technology advances and gate oxides of transistors are scaled down, breakdown of the oxide and reliability become a concern. Higher electric fields in the oxide increase the tunneling of carriers from the channel into the oxide, causing a charge buildup. Since the gate oxide is relatively thin, this charge buildup can destroy the gate oxide, thereby degrading transistor performance. FIG. 2 schematically illustrates this charge buildup on a gate of a logic module 103. Logic modules 102 and 103 may be part of a multi-level device. In the example of FIG. 2, interconnect lines 104 and 106 may be formed on a first metal level (also referred to as “M1”), while interconnect line 105 may be formed on a second metal level (also referred to as “M2”) above the first metal level. The formation of interconnect line 105 by PVD may result in charge buildup on interconnect line 106, which may damage module 103 and other circuits connected to interconnect line 106. This is a problem in semiconductor manufacturing processes, and may result in low yield.
A conventional technique to guard against damage to gates due to charge buildup is shown in the schematic diagram of FIG. 3. The conventional technique involves the use of reverse bias diodes, where the reverse breakdown and leakage characteristics are relied upon to discharge the accumulated charge on the gates. In FIG. 3, a diode 302 serves to protect the gate of transistor 303 from charge buildup on interconnect line 301 during a PVD process. To be effective, this technique may require the use of many diodes per interconnect line (also referred to as a “net” in a layout). The graph of FIG. 4 shows the number of diodes (also referred to as “antenna cells” or “antenna diodes”) as a function of a number of nets for an example device. The first data point indicates there are 97 nets that require only 1 diode, the last data point indicates there are 6 nets that require 25 diodes, and data point 410 indicates that there are 3 nets that require 23 diodes. FIG. 5 schematically shows a layout of a conventional solution showing the relatively high number of diode cells 504 required in one exemplary embodiment. In the example of FIG. 5, five diode cells 504 protect a gate (not shown) connected to interconnect line 502, which in turn is coupled to diode cells 504 by way of interconnect lines 506 and 508. FIG. 6 shows the equivalent schematic diagram for diode cells 504. The ratio of the amount of metal area of the interconnect line to the amount of gate area to be protected determines how many diodes need to be placed on the interconnect line. Many diodes may need to be placed on long nets. These diodes load the net and continue to leak charge even during normal operation. They are costly in terms of area, power and signal propagation delay.